1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a multilayer wiring structure, a semiconductor integrated circuit wiring method, and a cell arranging method. More particularly, the present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit wiring technology, which are capable of achieving reduction in signal delay and improvement in noise resistibility in the semiconductor integrated circuit in which a wiring layer formed using oblique wiring grid is stacked on a wiring layer formed using X-Y wiring grid.
2. Related Art
As the multilayer wiring structure of an LSI according to the standard cell method or the gate array method in the prior art, there has been employed a method of stacking wiring layers, which are intersected orthogonally with each other, sequentially as an upper layer. In other words, the n-th layer is provided to intersect orthogonally with the (nxe2x88x921)-th layer, e.g., the second layer is intersected orthogonally with the first layer, the third layer is intersected orthogonally with the second layer, so on. In such multilayer wiring structure in which respective layers are provided to intersect orthogonally with each other, if two points are to be connected along the diagonal direction of LSI, the points which are separated by a Euclidean distance must be connected. Therefore, a wiring which has a length in excess of a {square root over (2)} times distance of a linear distance is needed. Accordingly, in the orthogonal type multilayer wiring structure, overhead is caused in both an integration density and a delay characteristic.
However, an approach for designing wirings on the orthogonal coordinate system is convenient for an algorithm in LSI wiring design by using a computer. Therefore, the wirings have been designed by the computer without regard for the above overhead.
Meanwhile, with the progress of microfabrication of the circuit structure, an overall circuit performance is swayed by a delay component generated due to the wiring structure. Therefore, it has been impossible to disregard the above overhead caused when the wiring length is provided longer, as described above.
More particularly, first, a delay component due to the wiring resistance occupies the most part of the critical path delay. In this manner, an influence of the wiring length upon the circuit performance is now increasing.
Also, second, a coupling capacitance between neighboring wirings out of a load capacitance due to the wiring becomes dominant rather than a capacitance between the wiring and a substrate. As a result, in order to improve the circuit performance, it becomes an important factor how to reduce the capacitance between the neighboring wirings.
In addition, third, a malfunction which is caused by the coupling noise due to the coupling capacitance between the neighboring wirings becomes more serious. Particularly, in the wiring structure in the prior art in which all wirings are provided to intersect orthogonally with each other, if the neighboring wirings which are provided to extend in parallel in the same wiring layer are affected mutually, the upper and lower wirings are also extended in parallel even when the wiring is replaced with a wiring being placed in another wiring layer. For this reason, it is difficult to reduce the coupling capacitance between the wirings which are extended in parallel in the same wiring layer.
In connection with the orthogonal type multilayer wiring structure, there has been proposed an oblique wiring technology in which lengths of the wirings are reduced by using the oblique wirings (an oblique angle is 45xc2x0 or 135xc2x0 ) in addition to the orthogonal wiring structure. For example, such oblique wiring technology has been disclosed in xe2x80x9cAn automatic layout method of a semiconductor integrated circuitxe2x80x9d set forth in Patent Application Publication (KOKAI) Hei 5-102305. This prior art will be explained hereinbelow.
FIG. 1 is a view showing a layout of a wiring grid structure of a semiconductor integrated circuit device utilizing the oblique wirings in the prior art.
In this wiring grid structure, oblique wiring grids are formed as other layers on a layer which constitutes the orthogonal coordinates. In FIG. 1, a reference 401 denotes a wiring grid of a first layer. A wiring grid 402 of a second layer is formed on the first layer to orthogonally intersect with the first layer. In addition, a wiring grid 403 of a third layer is formed on the second layer 402 in the 45xc2x0 oblique direction relative to the first layer 401, and a wiring grid 404 of a fourth layer is formed on the third layer in the 135xc2x0 oblique direction relative to the first layer 401.
However, in the prior art, the multilayer wiring technology utilizing the oblique wirings has had problems as follows.
(1) In the multilayer wiring structure in the prior art, since the oblique wiring grid is provided simply, there has been a problem of a discrepancy between grid points. In other words, as shown in FIG. 2, a grid point formed by the first layer 401 and the second layer 402 is indicated by a reference 501 in FIG. 2. While, a grid point formed by the third layer 403 and the fourth layer 404 is indicated by a reference 502. In this case, if a contact hole (via hole) is formed from the fourth layer 404 to the third layer 403, such hole is provided at the grid point 502. On the other hand, if a via hole is formed from the third layer 403 to the second layer 402, such hole is provided at the grid point 501. However, if the grid point 501 is located in the close vicinity of the grid point 502, no via hole can be provided, so that the via hole must be provided at another position. In this way, since discrepancy of the grid points is caused between the overlying oblique wiring lattices (the third layer 403 and the fourth layer 404) and the underlying X-Y wiring lattices (the first layer 401 and the second layer 402), the wiring design has become complicated.
(2) A resistance of the overlying oblique wiring layer becomes equal to the underlying wiring layer. Therefore, even if the oblique wiring layer is employed as the overlying layer, RC delay due to the wiring cannot be reduced. Where the term xe2x80x9cRC delayxe2x80x9d is delay which is generated by a resistance component R and a capacitance component C. For this reason, the wiring structure which is fitted for the global wiring to connect a long distance cannot be implemented by the overlying oblique wiring layer.
(3) Normally a wiring pitch of the overlying oblique wiring layers is not set wider than a minimum design rule. Therefore, the structure for reducing the neighboring wiring capacitance cannot be achieved by arranging the oblique wiring layer as the overlying layer. As for this respect, the second technology has been disclosed in Patent Application Publication (KOKAI) Hei 7-86414. According to the second technology, wirings located in the layer on which the most severe limitation of a wiring distance by the design rule is imposed are arranged obliquely with respect to the wiring grid on CAD. However, because this prior art cannot provide such a structure that a wiring width is not set wide simultaneously, the above wiring resistance cannot be reduced. In addition, because the coupling capacitance between the neighboring wirings is not reduced, RC delay of the wiring cannot be reduced.
(4) In the prior art, a profile of the via hole is defined as a rectangle. However, if the wirings other than the orthogonal wirings, i.e., the obliquely intersected wirings are connected mutually, it is impossible to assure a necessary and sufficient cut area by the rectangular via hole. Hence, sufficient resistibility for the electromigration phenomenon which brings about disconnection defect of the wiring has not been achieved.
(5) A relationship between the definition of a cell row which is formed by aligning logic cells in a row and the definition of an oblique wiring grid has not been made clear. Therefore, in the event that four wiring layers of two orthogonal wiring layers and two oblique wiring layers, for example, are defined in total, it is evident that wiring resources to be positioned in parallel with the cell row are insufficient. As for this respect, in Patent Application Publication (KOKAI) Hei 5-243379 entitled xe2x80x9cSemiconductor Integrated Circuit Devicexe2x80x9d, the technology has been disclosed which can overcome the problem of lack of the wiring resources by defining two oblique wiring layers on three orthogonal wiring layers. However, there has been a problem that, since this technology needs five wiring layers, increase in the cost is caused.
(6) It has been impossible to reduce the cross talk noise, which brings about a malfunction of the circuit, in the same wiring layer. According to the wiring structure having the oblique wiring grid in the prior art, overlying and underlying wiring layers are not overlapped in the same wiring direction. As a result, the coupling capacitance between the wirings formed on the overlying and underlying wiring layers can be reduced small, and therefore the problem of the cross talk noise between the overlying and underlying wiring layers can be overcome. However, since different wirings are formed in parallel on the same wiring layer, the coupling capacitance between the neighboring wirings cannot be reduced. In other words, according to the oblique wiring grid technology in the prior art, it has been impossible to remove the cross talk noise which is generated between two parallel wirings formed on the same wiring layer.
(7) The oblique wiring grid in the prior art is not enough to form the power supply wiring. For instance, in the case that a pad is formed in a core area of the chip constituting a combinational circuit, a part of the pad can be employed as the power supply wiring. (In contrast to the core area, a peripheral area in which I/O of the chip are provided is called an xe2x80x9cI/O areaxe2x80x9d.) In this case, the overlying oblique wiring grid layer can be employed as an auxiliary power supply wiring. In such structure, the oblique wiring grid structure in the prior art has a wiring pitch or a wiring width which is not fitted to form a wider wiring. Therefore, such structure has been unsuitable to utilize the overlying oblique wiring grid layer effectively as the power supply wiring.
(8) Since a wiring length of the wiring for supplying a clock from PLL (Phase Locked Loop) to flip-flops in the chip is long, delay has been increased.
Normally, the PLL is arranged on a corner for avoiding aggravation of characteristics of built-in analog circuit in the chip, and then wirings are provided from this corner to the flip-flops. Hence, the wiring which has a length as the shortest route close to a half peripheral length of the chip must be drawn. Accordingly, the delay is increased and the number of steps of the buffer is also increased, whereby a duty ratio of the clock has been badly influenced.
(9) In the case of a memory circuit such as SRAM, since the coupling noise is generated between wirings in the memory circuit and wirings passing over the memory circuit, a performance of the memory circuit is degraded by the passing wirings. Therefore, in the prior art, wiring designs have been conducted so as to avoid the passing wirings which are provided over the memory circuit.
In prior art, there is one technology for shielding the passing wirings which are provided over the memory circuit. However, according to this technology, another layer has also been needed to shield the wirings. As a result, the circuit structure has become complicated.
In addition, in the prior art, there is another technology which employs the passing wirings provided over the memory circuit as small amplitude signal wirings. However, according to this technology, the applicable integrated circuit has been limited.
The present invention has been made to overcome the above problems in the prior art. It is an object of the present invention to provide a semiconductor integrated circuit device and a semiconductor integrated circuit wiring method, which are able to improve delay characteristic and noise resistibility of a circuit and also achieve facility of wiring design and reduction in production cost by utilizing oblique wiring layers in the semiconductor integrated circuit which employs a multilayer wiring structure in which oblique wiring grids being intersected orthogonally with each other in the oblique direction are provided in addition to wiring grids being intersected orthogonally with each other in the X-Y direction.
According to an aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a semiconductor area in which a plurality of unit elements are formed; a reference wiring layer which is formed over the semiconductor area and in which an X-Y reference wiring grid comprises a total of M (Mxe2x89xa72) layers where an n-th (nxe2x89xa72) layer wiring intersects orthogonally with a (nxe2x88x921)-th layer wiring; and an oblique wiring layer which is positioned over the reference wiring layer and in which an oblique wiring grid which intersects with the reference wiring grid to have an angle of 45 degree or 135 degree, the oblique wiring grid comprising a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other; wherein each one of the (m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring layer has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring layer, and a wiring width of {square root over (2)} times of that of respective layer in the reference wiring layer.
Preferably the reference wiring layer is composed of two layers or three layers. If the reference wiring layer is composed of three layers, the first layer wirings and the third layer wirings are provided in parallel with the cell row.
Preferably wirings of the oblique wiring layer are employed as global wirings.
According to another aspect of the present invention, the reference wiring layer and the oblique wiring layer constitute routing channel area, and the routing channel area is provided in parallel with a cell row in which logic cells formed of the unit elements are aligned in a row.
According to another aspect of the present invention, via hole for connecting the wirings, being formed at intersecting positions between wiring in the reference wiring layer and wiring in the oblique wiring layer, and the via hole has a sectional shape formed of any one of a hexagon, an octagon, and a parallelogram.
According to another aspect of the present invention, the plurality of unit elements constitute a cell, and the cell has obstruction area which is defined along wiring directions of the oblique wiring layer and in which wiring is not provided.
According to another aspect of the present invention, a part of the wiring of the oblique wiring layer is formed as a power supply wiring for supplying a power supply voltage.
According to another aspect of the present invention, the plurality of unit elements constitute cell which is supplied with a clock signal via tree type wiring route, and the tree type wiring route is constructed by combining unit wiring structures which is formed by connecting first wiring, which is formed by route extended on the wiring of the oblique wiring layer from a first point and a second point so as to come close to each other, and second wiring, which is formed by routes extended on the wiring of the oblique wiring layer from a third point and a fourth point so as to come close to each other, via the wiring in the reference wiring layer.
According to another aspect of the present invention, the semiconductor integrated circuit device further comprising: a flip-flop circuit; and a PLL (Phase Locked Loop) arranged at a corner of a chip; wherein the flip-flop circuit is supplied with a clock signal via tree type wiring route, and the tree type wiring route is provided from the PLL to a center of the chip by using wiring of the oblique wiring layer, and then wiring is hierarchically provided from the center of the chip to the flip-flop circuits via buffer cell so as to balance an RC product.
According to another aspect of the present invention, the semiconductor integrated circuit device further comprising: an SRAM circuit in which wiring of the reference wiring layer is used as its inner wiring; and wherein wiring passing over the SRAM circuit is provided in the oblique wiring layer.
According to another aspect of the present invention, there is provided a method of wiring elements of a semiconductor integrated circuit, comprising the steps of: forming an X-Y reference wiring layer constituting a total of M (Mxe2x89xa72) layers in which an n-th (nxe2x89xa72) layer wiring intersects orthogonally with a (nxe2x88x921)-th layer wiring; and forming an oblique wiring layer which is positioned over the reference wiring layer to have an angle of 45 degree or 135 degree, the oblique wiring layer comprising a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that each one of (m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring layer has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring layer, and a wiring width of {square root over (2)} times of that of respective layers in the reference wiring layer.
According to another aspect of the present invention, the method further comprising the steps of: extracting wiring nets which delay in excess of a prescribed delay time from wiring nets constructed by the wiring in the reference wiring layer; and inserting signal amplifying buffer cell into a position, which can be connected to wiring of the oblique wiring layer, on the extracted wiring nets.
According to another aspect of the present invention, the method further comprising the steps of: when one wiring of two parallel wirings, which correspond to two wirings of the M layers of the reference wiring lattice and belong to a same layer, generates noises onto other wiring, replacing a prescribed portion in a middle of any one wiring of two wirings with wiring of the oblique wiring layer.
According to another aspect of the present invention, there is provided a method of arranging cells on a semiconductor integrated circuit, comprising the steps of: forming an X-Y reference wiring layer constituting a total of M (Mxe2x89xa72) layers in which an n-th (nxe2x89xa72) layer wiring intersects orthogonally with a (nxe2x88x921)-th layer wiring; forming an oblique wiring layer which is positioned over the reference wiring layer to have an angle of 45 degree or 135 degree, the oblique wiring layer comprising a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that each one of (m+1) -th layer wiring and(m+2)-th layer wiring in the oblique wiring layer has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring layer; and arranging cell consisting of a plurality of unit elements based on a prescribed cut method utilizing X-Y cut lines which correspond to wiring directions of the reference wiring layer and oblique cut lines which correspond to wiring directions of the oblique wiring layer.
According to another aspect of the present invention, there is provided a method of wiring elements of a semiconductor integrated circuit, comprising the steps of: forming an X-Y reference wiring layer constituting a total of M (mxe2x89xa72) layer in which an n-th (nxe2x89xa72) layer wiring intersects orthogonally with a (nxe2x88x921)-th layer wiring; forming an oblique wiring layer which is positioned over the reference wiring layer to have an angle of 45 degree or 135 degree, the oblique wiring layer comprising a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that each one of (m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring layer has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring layer; providing wiring from a PLL (Phase Locked Loop) arranged at a corner of a chip to a center of the chip, by using wiring of the oblique wiring layer; and providing hierarchically wiring from the center of the chip to flip-flop circuits in the chip via buffer cells so as to balance an RC product.
According to another aspect of the present invention, there is provided a method of wiring elements of a semiconductor integrated circuit, comprising the steps of: forming an X-Y reference wiring layer constituting a total of M (Mxe2x89xa72) layers in which an n-th (nxe2x89xa72) layer wiring intersects orthogonally with a (nxe2x88x921)-th layer wiring; forming an oblique wiring layer which is positioned over the reference wiring layer to have an angle of 45 degree or 135 degree, the oblique wiring layer comprising a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that each one of (m+1)-th layer wiring and(m+2)-th layer wiring in the oblique wiring layer has a wiring pitch of {square root over (2)} times of that of wiring in the reference wiring layer; forming an SRAM circuit in which wiring of the reference wiring layer is used as its inner wiring; and forming wiring, which is passed over the SRAM circuit, on the oblique wiring layer.